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november 2002 dav digital audio/speaker data manual sles041b
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third?party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2002, texas instruments incorporated
contents iii november 2002 sles041b contents section page 1 introduction 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 functional block diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 terminal assignments 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 ordering information 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 terminal functions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 architecture overview 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 clock and serial data interface 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 normal-speed, double-speed, and quad-speed selection 6 . . . . . . . . . . . . . . . . . . . 2.1.2 clock master/slave mode (m_s) 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 clock master mode 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.4 clock slave mode 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.5 pll filter 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.6 dclk 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.7 serial data interface 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 reset, power down, and status 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 reset ? reset 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 power down ? pdn 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 status registers 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 signal processing 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 volume control 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 mute 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 auto mute 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 individual channel mute 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 de-emphasis filter 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 pulse width modulator (pwm) 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 clipping indicator 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 error recovery 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 individual channel error recovery 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.4 pwm dc-offset correction 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.5 inter-channel delay 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.6 pwm/h-bridge and discrete h-bridge driver interface 20 . . . . . . . . . . . . . . . . . . . . . . . 2.5 i2c serial control interface 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 single byte write 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 multiple byte write 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 single byte read 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 multiple byte read 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 serial control interface register definitions 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 general status register (x00) 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 error status register (x01) 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 system control register 0 (x02) 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 system control register 1 (x03) 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 error recovery register (x04) 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 automute delay register (x05) 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 dc-offset control registers (x06 ? x0b) 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 interchannel delay registers (x0c ? x11) 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
list of illustrations iv november 2002 sles041b 3.9 individual channel mute register (x19) 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 system initialization 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 specifications 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 absolute maximum ratings over operating temperature ranges 29 . . . . . . . . . . . . . . . . . . . . . . . 5.2 recommended operating conditions 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 electrical characteristics 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 static digital specifications 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 digital interpolation filter and pwm modulator 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 TAS5026/tas5100 system performance measured at the speaker terminals 30 . . . 5.4 switching characteristics 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 command sequence timing 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 serial audio port 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 serial control port ? i2c operation 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 application information 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 serial audio interface clock master and slave interface configuration 39 . . . . . . . . . . . . . . . . . . . 6.1.1 slave configuration 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 master configuration 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 mechanical data 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . list of illustrations figure title page 2 ? 1 crystal circuit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 external pll loop filter 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 3 i2s 64-fs format 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 4 i2s 48-fs format 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 5 left-justified 64-fs format 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 6 left-justified 48-fs format 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 7 right-justified 64-fs format 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 8 right-justified 48-fs format 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 9 dsp format 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 10 attenuation curve 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 11 de-emphasis filter characteristics 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 12 pwm outputs and h-bridge driven in btl configuration 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 13 typical i2c sequence 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 14 single byte write transfer 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 15 multiple byte write transfer 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 16 single byte read 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 17 multiple byte read 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 1 reset during system initialization 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 1 reset timing 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 2 power-down and power-up timing ? reset preceding pdn 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 3 power-down and power-up timing ? reset following pdn 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 4 error recovery timing 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 5 mute timing 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
list of tables v november 2002 sles041b 5 ? 6 right-justified, iis, left-justified serial protocol timing 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 7 right, left, and iis serial mode timing requirement 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 8 serial audio ports master mode timing 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 9 dsp serial port timing 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 10 dsp serial port expanded timing 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 11 dsp absolute timing 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 12 scl and sda timing 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 13 start and stop conditions timing 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 1 typical TAS5026 application 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 2 TAS5026 serial audio port ? slave mode connection diagram 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 3 TAS5026 serial audio port ? master mode connection diagram 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . list of tables table title page 2 ? 1 normal-speed, double-speed, and quad-speed operation 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 master and slave clock modes 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 3 lrclk, mclk_in, and external pll rates 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 4 dclk 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 5 supported word lengths 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 6 device outputs during reset 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 7 values set during reset 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 8 device outputs during power down 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 9 volume register 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 10 de-emphasis filter characteristics 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 11 device outputs during error recovery 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 1 i2c register map 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 2 general status register (read only) 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 3 error status register 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 4 system control register 0 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 5 system control register 1 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 6 error recovery register 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 7 automute delay register 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 8 dc-offset control registers 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 9 six inter-channel delay registers 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 10 individual channel mute register 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
introduction 1 sles041b?november 2002 TAS5026 1 introduction the TAS5026 is an innovative, cost-effective, high-performance 24-bit six-channel digital pulse width modulator (pwm) based on equibit ? technology. combined with a ti digital amplifier power stage, these devices use noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. the TAS5026 is designed to drive up to six digital power devices to provide six channels of digital audio amplification. the digital power devices can be six conventional monolithic power stages (such as tas5110) or six discrete differential power stages using gate drivers and mosfets. the TAS5026 has six independent volume controls and mute. it is designed to drive a digital amplifier power stage (such as the tas5182) in an h-bridge (bridge tied load) configuration. the device operates in ad mode. this all-digital audio system contains only two analog components in the signal chain ? an lc low-pass filter at each speaker terminal and can provide up to 96-db snr at the speaker terminals. the TAS5026 has a wide variety of serial input options including right justified (16, 20, or 24 bit), i2s (16, 20, or 24 bit) left justified, or dsp (16-bit) data formats. the device is fully compatible with aes standard sampling rates of 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz, and 192 khz including de-emphasis for 44.1-khz and 48-khz sample rates. the TAS5026 was designed for home theater applications such as dvd minicomponent systems, home theater in a box (htib), dvd receiver, a/v receiver, or tv sets. 1.1 features ? true digital audio amplifier ? high quality audio ? 96-db snr ? <0.1% thd+n ? six-channel volume control ? patented soft volume ? patented soft mute ? 16-, 20-, or 24-bit input data ? sampling rates: 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz, and 192 khz ? supports master and slave modes ? 3.3-v power supply operation ? economical 64-pin tqfp package ? digital de-emphasis: 32 khz, 44.1 khz, and 48 khz ? high power efficiency ? clock oscillator circuit for master modes ? low jitter internal pll ? soft volume and mute update ? excellent psrr equibit is a trademark of texas instruments incorporated.
introduction 2 sles041b ? november 2002 TAS5026 1.2 functional block diagram pwm ch. output control avdd_pll avss_pll vrega_cap vregb_cap vregc_cap dvdd_rcl dvss_rcl dvdd_pwm dvss_pwm power supply pll_flt_out pll_flt_ret sclk lrclk mclkout sdin1 sdin2 sdin3 mclk_in xtal_out xtal_in css sda scl cso pwm_ap_1 valid_1 pwm_ap_2 valid_2 pwm ap_3 valid_3 pwm_ap_4 valid_4 pwm_ap_5 valid_5 pwm_ap_6 valid_6 pwm am_3 pwm_am_1 pwm_am_2 pwm_am_4 pwm_am_5 pwm_am_6 clock, pll and serial data i/f pdn reset mute clip err_rcvy serial control i/f reset, pwr dwn and status auto mute de-emphasis soft volume error recovery soft mute clip detect signal processing pwm section pwm ch. pwm ch. pwm ch. pwm ch. pwm ch. m_s
introduction 3 sles041b ? november 2002 TAS5026 1.3 terminal assignments 17 dvdd_rcl dvss_rcl nc dvdd_pwm dvss_pwm pwm_ap_4 pwm_am_4 valid_4 pwm_ap_5 pwm_am_5 valid_5 pwm_ap_6 pwm_am_6 valid_6 nc nc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc mclk_in avdd_pll pll_flt_out pll_flt_ret avss_pll nc dvss1 rst err_rcvy mute pdn sda scl cs0 dvss1 18 19 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pag package (top view) dbspd clip sdin1 sdin2 sdin3 mclk_out sclk lrclk dvdd dvss1 nc dem_sel2 dem_sel1 m_s dvss1 dvss1 avdd_osc xtl_in xtl_out avss_osc dvss pwm_ap_1 pwm_am_1 valid_1 pwm_ap_2 pwm_am_2 valid_2 pwm_ap_3 pwm_am_3 valid_3 nc nc 20
introduction 4 sles041b ? november 2002 TAS5026 1.4 ordering information texas instruments t as audio solutions 5026 c pag device number temperature range package type available options package t a plastic 64-pin tqfp (pag) 0 c to 70 c TAS5026cpag ? 40 c to 85 c TAS5026ipag 1.5 terminal functions terminal i/o description name no. i/o description avdd_osc 64 pwr analog power supply for internal oscillator cells avdd_pll 3 pwr 3.3-v analog power supply for pll avss_osc 61 aout analog ground for internal oscillator cells avss_pll 6 pwr analog ground for pll clip 18 o digital clipping indicator, active low cs0 15 i i 2 c device address select. this is an active high pin. dbspd 17 i sample rate is double speed (88.2 khz or 96 khz), active high dm_sel1 29 i de-emphasis select bit 1 (0 = none, 01 = 32 khz, 10 = 44.1 khz dm_sel2 28 i de-emphasis select bit 2, 10 = 48 khz, 11= undefined (none) dvdd_pwm 45 pwr 3.3-v digital power supply for pwm dvdd_rcl 48 pwr 3.3-v digital power supply for re-clocker dvdd 25 pwr 3.3-v digital power supply for digital core and most of i/o buffers dvss 60 i voltage regulator enable, active low dvss_pwm 44 pwr digital ground for pwm dvss_rcl 47 pwr digital ground for re-clocker dvss1 8, 26, 31, 32 pwr digital ground for digital core and most of i/o buffers err_rcvy 10 i error recovery, active low lrclk 24 i/o serial audio data left / right clock (sampling rate clock) (input when m_s = 0; output when m_s = 1) m_s 30 i master/slave mode input signal (master = 1, slave = 0) mclk_in 2 i mclk input, slave mode mclk_out 22 o mclk output buffered system clock output m_s = 1; otherwise set to 0
introduction 5 sles041b ? november 2002 TAS5026 terminal description i/o name description i/o no. mute 11 i mute input signal, active low nc 1, 7, 27, 49, 50 no connection pdn 12 i power down. this signal is active low. pll_flt_out 4 i pll external filter pll_flt_ret 5 i pll external filter pwm_am_1 58 o pwm 1 output (differential -); {positive h-bridge side} pwm_am_2 55 o pwm 2 output (differential -); {positive h-bridge side} pwm_am_3 52 o pwm 3 output (differential -); {positive h-bridge side} pwm_am_4 42 o pwm 4 output (differential -); {positive h-bridge side} pwm_am_5 39 o pwm 5 output (differential -); {positive h-bridge side} pwm_am_6 36 o pwm 6 output (differential -); {positive h-bridge side} pwm_ap_1 59 o pwm 1 output (differential +); {positive h-bridge side} pwm_ap_2 56 o pwm 2 output (differential +); {positive h-bridge side} pwm_ap_3 53 o pwm 3 output (differential +); {positive h-bridge side} pwm_ap_4 43 o pwm 4 output (differential +); {positive h-bridge side} pwm_ap_5 40 o pwm 5 output (differential +); {positive h-bridge side} pwm_ap_6 37 o pwm 6 output (differential +); {positive h-bridge side} rst 9 i system reset input. this signal is an active low. scl 14 i i2c clock signal sclk 23 i/o serial audio data clock (master mode = output, slave mode = input) sda 13 i/o i2c data signal sdin1 19 i serial audio data 1 input sdin2 20 i serial audio data 2 input sdin3 21 i serial audio data 3 input valid_1 57 o output indicating validity of pwm outputs, channel 1, active high valid_2 54 o output indicating validity of pwm outputs, channel 2, active high valid_3 51 o output indicating validity of pwm outputs, channel 3, active high valid_4 41 o output indicating validity of pwm outputs, channel 4, active high valid_5 38 o output indicating validity of pwm outputs, channel 5, active high valid_6 35 o output indicating validity of pwm outputs, channel 6, active high xtl_in 63 ain crystal or ttl level clock input xtl_out 62 aout crystal output (not for external usage)
architecture overview 6 sles041b ? november 2002 TAS5026 2 architecture overview the TAS5026 is composed of six functional elements: ? clock, pll, and serial data interface (iis) ? reset/power down circuitry ? serial control interface (iic) ? signal processing unit ? pulse width modulator (pwm) ? power supply 2.1 clock and serial data interface the TAS5026 clock and serial data interface contains an input serial data slave and the clock master/ slave interface. the serial data slave interface receives information from a digital source such as a dsp, s/pdif receiver, analog-to-digital converter (adc), digital audio processor (dap) such as the tas3103, or other serial bus master at sample rates of for sample rates of 32 khz, 44.1 khz, 48 khz, 88.2 khz, 96 khz,176.4 khz, and 192 khz. the serial data interface has three serial data inputs that can accept up to six channels of data. the serial data interfaces support left justified and right justified for 16-, 20-, and 24-bits. in addition, the serial data interfaces support the dsp protocol for 16 bits and the i2s protocal for 24 bits. the received data is data passed to the TAS5026 signal-processing unit. the TAS5026 can function as a receiver or a generator for the mclk_in (master clock), sclk (shift clock), and lrclk (left/right clock) signals that control the flow of data on the three serial data interfaces. the TAS5026 is a clock master when it generates these clocks and is a clock slave when it receives these clocks. the TAS5026 is a synchronous design that relies upon master clock to provide a reference clock for all of the device operations. when operating as a slave, this reference clock is mclk_in. when operating as a master, the reference clock is either ttl clock input to xtal_in or a crystal attached across xtal_in and xtal_out. if the master clock stops, the TAS5026 will perform a clock error recovery sequence. the clock error recovery sequence temporarily suspends processing, places the pwm outputs in a hard mute (pwm_p outputs are low; pwm_m outputs are high, and all valid signals are low), resets all internal processes, sets the volumes to mute, and suspends all i 2 c operations. when the master clock is resumed, the TAS5026 exits the clock error recovery sequence by performing a 4.3-ms partial re-initialization, noiselessly restarting the pwm output, and ramping the volume up to the level specified in the volume control registers. the volume update is performed over a 43-ms. interval. the TAS5026 preserves all control register settings that were set prior to the clock interruption. if a clock error occurs while the err_rcvry pin is asserted (low), the TAS5026 will perform the error recovery sequence up to the unmute sequence. in this case, the volume remains at full attenuation with the pwm output at a 50% duty cycle. the volume can be restored from this state by triggering a mute/unmute sequence via the mute pin low then high. the clock and serial data interface has two control parameters: data sample rate and clock master or slave. 2.1.1 normal-speed, double-speed, and quad-speed selection the sampling rate is selected through a pin (dbspd) or the serial control register 0 (x02). when a sample rate is selected, the system automatically performs an error recovery sequence and switches to the new sampling rate. as shown in subsequent sections, the sample rate control sets the frequencies of the sclk and lrclk in clock slave mode and the output frequencies of sclk and lrclk in clock master mode. during the error recovery sequence, the TAS5026 temporarily suspends processing, places the pwm outputs in a hard mute (pwm p outputs low; pwm m outputs high, and all valid signals low), resets all internal processes, and suspends all i 2 c operations. the TAS5026 then performs a 4.3-ms partial re-initialization and noiselessly restarts the pwm output. the TAS5026 preserves all control register settings through out the error recovery sequence.
architecture overview 7 sles041b ? november 2002 TAS5026 there are three data rates: normal speed, double speed, and quad speed. normal-speed mode supports data rates of 32 khz, 44.1 khz, and 48 khz. normal speed is supported in the master and slave modes. the pwm is placed in normal speed by setting the dbspd terminal low or by setting the normal mode bits in the system control register through the serial control interface. following this operation, the pwm performs an error recovery sequence automatically and operates in the normal speed mode. double-speed mode is used to support sampling rates of 88.2 khz and 96 khz. double speed is supported in master and slave modes. the pwm is placed in double speed mode by setting the dbspd terminal high or by setting the double speed bits in the system control register through the serial control interface. following this operation, the pwm performs an error recovery sequence automatically and operate in double speed mode. quad-speed mode is used to support sampling rates of 176.4 khz and 192 khz. quad-speed mode is auto detected supported in slave mode and invoked by control in master mode in slave mode, if the device is not in double speed mode, quad-speed mode is automatically detected when mclk_in is 128fs. in master mode, the pwm is placed in quad-speed mode by setting the quad-speed bit in the system control register through the serial control interface. table 2?1. normal-speed, double-speed, and quad-speed operation quad-speed control register bit dbspd terminal or control register bit mode speed selection 0 0 master or slave normal speed 0 1 master or slave double speed 1 0 master or slave quad speed 0 0 slave quad speed if mclk_in = 128fs 1 1 master or slave error 2.1.2 clock master/slave mode (m_s) clock master and slave mode can be invoked using the m_s (master slave) terminal. this terminal specifies the default mode that is set immediately following a device reset. the serial data interface setting permits the clock generation mode to be changed during normal operation. the transition to master mode occurs: ? following a reset when m_s terminal has a logic high applied the transition to slave mode occurs: ? following a reset when m_s terminal has a logic low applied 2.1.3 clock master mode when m_s = 1 following a reset, the TAS5026 provides the master clock, sclk, and lrclk to the rest of the system. in the master mode, the TAS5026 outputs the audio system clocks mclk_out, sclk, and lrclk. the TAS5026 device generates these clocks plus its internal clocks from the internal phase-locked loop (pll). the reference clock for the pll can be provided by either an external clock source (attached to xtal_in) or a crystal (connected across terminals xtal_in and xtal_out). the external source attached to mclk_in is 256 times (128 in quad mode) the data sample rate (fs). the sclk frequency is 64 times the data sample rate and the sclk frequency of 48 times the data sample rate is not supported in the master mode. the lrclk frequency is the data sample rate. 2.1.3.1 crystal type and circuit in clock master mode the TAS5026 can derive the mclkout, sclk, and lrclk from a crystal. in this case, the TAS5026 uses a parallel-mode fundamental-mode crystal. this crystal is connected to the TAS5026 as shown in figure 2 ? 1.
architecture overview 8 sles041b ? november 2002 TAS5026 xo TAS5026 osc macro r d c 1 xi c 2 avss r d = drive level control resistor ? crystal vendor specified c l = crystal load capacitance (capacitance of circuitry between the two terminals of the crystal) c l = (c 1 x c 2 )/(c 1 + c 2 ) + c s (where c s = board stray capacitance ~ 3 pf) example: vendor recommended c l = 18 pf, c s = 3 pf c 1 = c 2 = 2 x (18 ? 3) = 30 pf figure 2 ? 1. crystal circuit 2.1.4 clock slave mode in the slave mode (m_s = 0), the master clock, lrclk, and sclk are inputs to the TAS5026. the master clock is supplied through the mclk_in terminal. as in the master mode, the TAS5026 device developed its internal timing from internal phase-locked loop (pll). the reference clock for the pll is provided by the input to the mclk_in terminal. this input is at a frequency of 256 times (128 in quad mode) the input data rate. the sclk frequency is 48 or 64 times the data sample rate. the lrclk frequency is the data sample rate. the TAS5026 does not require any specific phase relationship between srclk and mclk_in, but there must be synchronization. the TAS5026 monitors the relationship between mclk, sclk and lrclk. the TAS5026 detects if any of the three clocks are absent, if lrclk rate changes more the 10 mclk cycles since the last device reset or clock error recovery, or if mclk frequency is changing substantially with respect to the pll frequency. when a clock error is detected the TAS5026 performs a clock error recovery sequence. if one or more of the clock signals are absent, the TAS5026 is held with the outputs in hard mute until the clock is resumed. once the clock is resumed, the clock error recover sequence is completed. note: the detection of a clock error causes the TAS5026 to perform an immediate hard mute and suspension of all processes. this abrupt transition can produce a faint click as the outputs are muted. since the clocks are removed when changing media or during input selection, it is possible to use this knowledge to completely eliminate clicks in these conditions. in this case, the click is prevented by muting the outputs by using the mute terminal or the i 2 c /mute command 43 ms in advance of the clocks being removed. in the slave mode, mclk_out is driven low. table 2 ? 2 shows all the possible master and slave modes. when operating in quad mode (fs = 176.4 khz or 192 khz), the device works in slave mode only with mclk_in = 128 fs. table 2 ? 3 shows the clocks speed for normal, double and quad modes.
architecture overview 9 sles041b ? november 2002 TAS5026 table 2 ? 2. master and slave clock modes description m_s dbspd xtl_in (mhz) ? mclk_in (mhz) ? sclk (mhz) ? lrclk (khz) ? mclk_out (mhz) # internal pll, master, normal speed 1 0 8.192 - 2.048 32 8.192 internal pll, master, normal speed 1 0 11.2896 - 2.8224 44.1 11.2896 internal pll, master, normal speed 1 0 12.288 - 3.072 48 12.288 internal pll, master, double speed 1 1 - 22.5792 5.6448 88.2 22.5792 internal pll, master, double speed 1 1 - 24.576 6.144 96 24.576 internal pll, master, quad speed 1 0 - 22.5792 11.2896 176.4 22.5792 internal pll, master, quad speed 1 0 - 24.576 12.288 192 24.576 internal pll, slave, normal speed 0 0 - 8.192 2.0484 32 digital gnd internal pll, slave, normal speed 0 0 - 11.2896 2.8224 44.1 digital gnd internal pll, slave, normal speed 0 0 - 12.288 3.072 48 digital gnd internal pll, slave, double speed 0 1 - 22.5792 5.6448 88.2 digital gnd internal pll, slave, double speed 0 1 - 24.576 6.144 96 digital gnd internal pll, slave, quad speed || 0 0 - 22.5792 11.2896 176 digital gnd internal pll, slave, quad speed || 0 0 - 24.576 12.288 192 digital gnd external pll, master, normal speed 1 0 - - 2.048 32 8.192 external pll, master, normal speed 1 0 - - 2.8224 44.1 11.2896 external pll, master, normal speed 1 0 - - 3.072 48 12.288 external pll, master, double speed 1 1 - - 5.6448 88.2 22.5792 external pll, master, double speed 1 1 - - 6.144 96 24.576 external pll, master, quad speed 1 0 - - 11.2896 176.4 22.5792 external pll, master, quad speed 1 0 - - 12.288 192 24.576 external pll, slave, normal speed 0 0 - 8.192 2.0484 32 digital gnd external pll, slave, normal speed 0 0 - 11.2896 2.8224 44.1 digital gnd external pll, slave, normal speed 0 0 - 12.288 3.072 48 digital gnd external pll, slave, double speed 0 1 - 22.5792 5.6448 88.2 digital gnd external pll, slave, double speed 0 1 - 24.576 6.144 96 digital gnd external pll, slave, quad speed || 0 0 - 22.5792 11.2896 176 digital gnd external pll, slave, quad speed || 0 0 - 24.576 12.288 192 digital gnd ? a crystal oscillator is connected to xtl_in. ? mclk_in tied low when input to xtl_in is provided; xtl_in tied low when mclk_in_in is provided. external mclk_in connected to mclk_in_in input ? sclk and lrclk are outputs when m_s=1, and inputs when m_s=0. # mclk_out is driven low when m_s=0. || quad-speed mode is detected automatically. sclk can be 48 or 64 times fs table 2 ? 3. lrclk, mclk_in, and external pll rates normal speed (khz) double speed (khz) quad speed (khz) lrclk 1fs 32 44.1 48 1fs 64 88.2 96 1fs 176.4 192 mclk_in 256fs 8,192 11,289.6 12,288 256fs 16,384 22,579.2 24,576 128fs 22,579.2 24,576 ext. pll 2048fs 65,536 90,316.8 98,304 1024fs 65,536 90,316.8 98,304 512fs 90,316.8 98,304
architecture overview 10 sles041b ? november 2002 TAS5026 2.1.5 pll filter a low jitter pll produces the internal timing of the TAS5026 (when in master mode), the master clock, sclk, and lrclk. connections for the pll external loop filter are provided through pll_flt_out and pll_flt_ret as shown in figure 2 ? 2. pll_flt_out TAS5026 pll_flt_ret 220 ? 47 nf 4.7 nf figure 2 ? 2. external pll loop filter 2.1.6 dclk dclk is the internal high frequency clock that is produced by the pll circuitry from mclk. the TAS5026 uses the dclk to control all internal operations. dclk is 8 times the speed of mclk in normal speed mode, 4 times mclk in double speed, and 2 times mclk in quad speed. with respect to the i 2 c addressable registers, dclk clock cycles are used to specify interchannel delay and to detect when the mclk is frequency is drifting. table 2 ? 4 dclk shows the relationship between sample rate, mclk and dclk. table 2 ? 4. dclk fs (khz) mclk (mhz) dclk (mhz) dck period (ns) 32 8.1920 65.5360 15.3 44.1 11.2896 90.3168 11.1 48 12.2880 98.3040 10.2 88 22.5280 90.1120 11.1 96 24.5760 98.3040 10.2 192 49.1520 98.3040 10.2 2.1.7 serial data interface the TAS5026 operates as a slave only/receive only serial data interface in all modes. the TAS5026 has three pcm serial data interfaces to accept six channels of digital data though the sdin1, sdin2, sdin3 inputs. the serial audio data is in msb first; 2 ? s complement format. the serial data interfaces of the TAS5026 can be configured in right justified, i 2 s, left-justified, or dsp modes. this interface supports 32-khz, 44.1-khz, 48-khz, 88-khz, 96-khz, 176.4-khz, and 192-khz data sample rates. the serial data interface format is specified using the data interface control register. the supported word lengths are shown in table 2 ? 5. during normal operating conditions if the serial data interface settings change state, an error recovery sequence is initiated.
architecture overview 11 sles041b ? november 2002 TAS5026 table 2 ? 5. supported word lengths data modes word lengths mod2 mod1 mod0 right justified, msb first 16 0 0 0 right justified, msb first 20 0 0 1 right justified, msb first 24 0 1 0 i 2 s 16 0 1 1 i 2 s 20 1 0 0 i 2 s 24 1 0 1 left justified, msb first 24 1 1 0 dsp frame 16 1 1 1 2.1.7.1 i 2 s timing i 2 s timing uses an lrclk to define when the data being transmitted is for the left channel and when it is for the right channel. the lrclk is low for the left channel and high for the right channel. a bit clock running at 48 or 64 times fs is used to clock in the data. there is a delay of one bit clock from the time the lrclk signal changes state to the first bit of data on the data lines. the data is written msb first and is valid on the rising edge of the bit clock. the TAS5026 masks unused trailing data bit positions. master mode only supports a 64 times fs bit clock. 23 22 sclk 32 clks lrclk (note reversed phase) left channel 24-bit mode 9 8 5 4 1 0 19 18 20-bit mode 5 4 1 0 16-bit mode 1 0 15 14 msb lsb 23 22 sclk 32 clks right channel 9 8 5 4 1 0 19 18 5 4 1 0 1 0 15 14 msb lsb 2-channel i 2 s (philips format) stereo input figure 2 ? 3. i 2 s 64-fs format
architecture overview 12 sles041b ? november 2002 TAS5026 2-channel i 2 s stereo input/output (24-bit transfer word size) 23 22 sclk 24 clks lrclk left channel 24-bit mode 20 19 8 7 2 1 19 18 20-bit mode 16 15 1 0 16-bit mode 1 0 15 14 msb lsb 4 3 5 21 4 5 17 13 12 11 23 22 sclk 24 clks right channel 20 19 8 7 2 1 19 18 16 15 1 0 1 0 15 14 msb lsb 4 3 5 21 4 5 17 13 12 11 0 figure 2 ? 4. i 2 s 48-fs format 2.1.7.2 left-justified timing left-justified (lj) timing uses an lrclk to define when the data being transmitted is for the left channel and when it is for the right channel. the lrclk is high for the left channel and low for the right channel. a bit clock running at 48 or 64 times fs is used to clock in the data. the first bit of data appears on the data lines at the same time the lrclk toggles. the data is written msb first and is valid on the rising edge of the bit clock. the TAS5026 masks unused trailing data bit positions. master mode only supports a 64 times fs bit clock. 23 22 sclk 32 clks lrclk left channel 24-bit mode 9 8 5 4 1 0 msb lsb 2 -channel left-justified stereo input 23 22 32 clks lrclk right channel 9 8 5 4 1 0 msb lsb note: all data presented in 2s complement form with msb first. figure 2 ? 5. left-justified 64-fs format
architecture overview 13 sles041b ? november 2002 TAS5026 22 21 sclk 24 clks lrclk left channel 19 9 8 1 0 msb lsb 2-channel left-justified stereo input/output (24-bit transfer word size) 3 2 4 20 23 22 21 24 clks right channel 19 9 8 1 0 msb lsb 3 2 4 20 23 5 5 24-bit mode figure 2 ? 6. left-justified 48-fs format 2.1.7.3 right-justified timing right-justified (rj) timing uses an lrclk to define when the data being transmitted is for the left channel and when it is for the right channel. the lrclk is high for the left channel and low for the right channel. a bit clock running at 48 or 64 times fs is used to clock in the data. the first bit of data appears on the data 8-bit clock periods (for 24-bit data) after lrclk toggles. in rj mode, the last bit clock before lrclk transitions always clocks the lsb of data. the data is written msb first and is valid on the rising edge of bit clock. the TAS5026 masks unused leading data bit positions. master mode only supports a 64 times fs bit clock. 23 22 sclk 32 clks lrclk left channel 24-bit mode 19 18 15 14 1 0 19 18 20-bit mode 15 14 1 0 16-bit mode 1 0 15 14 msb lsb 2-channel right-justified (sony format) stereo input note: all data presented in 2s complement form with msb first. 23 22 32 clks right channel 19 18 15 14 1 0 19 18 15 14 1 0 1 0 15 14 msb lsb figure 2 ? 7. right-justified 64-fs format
architecture overview 14 sles041b ? november 2002 TAS5026 22 21 sclk 24 clks lrclk left channel 19 1 0 19 1 0 msb lsb 2-channel right-justified stereo input/output (24-bit transfer word size) 20 23 note: all data presented in 2s complement form with msb first. 1 0 8 9 15 14 18 18 8 9 8 9 15 14 15 14 22 21 24 clks right channel 19 1 0 19 1 0 msb lsb 20 23 1 0 8 9 15 14 18 18 8 9 8 9 15 14 15 14 24-bit mode 20-bit mode 16-bit mode figure 2 ? 8. right-justified 48-fs format 2.1.7.4 dsp mode timing dsp mode timing uses an lrclk to define when data is to be transmitted for both channels. a bit clock running at 64 fs is used to clock in the data. the first bit of the left channel data appears on the data lines following the lrclk transition. the data is written msb first and is valid on the rising edge of the bit clock. the TAS5026 masks unused trailing data bit positions. sclk lrclk 64 sclks lsb msb 16 bits left channel 16 bits right channel 32 bits unused sdin lsb msb figure 2 ? 9. dsp format
architecture overview 15 sles041b ? november 2002 TAS5026 2.2 reset, power down, and status the reset, power down, and status circuitry provides the necessary controls to bring the TAS5026 to the initial inactive condition, achieve low power standby, and report system status. 2.2.1 reset?reset the TAS5026 is placed in the reset mode by setting the reset terminal low. reset is an asynchronous control signal that restores the TAS5026 to its default conditions, sets the valid 1 ? 6 outputs low, and places the pwm in the hard mute state. volume is immediately set to full attenuation (there is no ramp down). as long as the reset terminal is held low, the device is in the reset state. during reset, all i 2 c and serial data bus operations are ignored. table 2 ? 6 shows the device output signals while reset is active. upon the release of reset , if power_dwn is high, the system performs a 4-ms to 5-ms device initialization and then ramps the volume up to 0 db using a soft volume update sequence. if mclk_in is not active when reset is released high, then a 4-ms to 5-ms initialization sequence is produced once mclk_in becomes active. during device initialization all controls are reset to their initial states. table 2 ? 7 shows the control settings that are changed during initialization. reset should be applied during power-up initialization or while changing the master slave clock states. table 2 ? 6. device outputs during reset signal mode signal state valid 1 ? valid 6 all low pwm p-outputs all low pwm m-outputs all low mclkout all low sclk master low sclk slave signal input lrclk master low lrclk slave signal input sda all signal input clip all high because the reset is an asynchronous control signal, small clicks and pops can be produced during the application (the leading edge) of this control. however, when reset is released, the transition from the hard mute state back to normal operation is performed synchronously using a quiet sequence. if a completely quiet reset sequence is desired, mute should be applied before applying reset . table 2 ? 7. values set during reset control setting volume 0 db mclk_in frequency 256 master/slave mode m_s terminal state auto mute enabled de-emphasis none dc offset 0 interchannel delay each channel set at 16 clocks higher then preceding channel
architecture overview 16 sles041b ? november 2002 TAS5026 2.2.2 power down ? pdn the TAS5026 can be placed into the power-down mode by holding the pdn terminal low. when power-down mode is entered, both the pll and the oscillator are shut down. volume is immediately set to full attenuation (there is no ramp down). the valid 1 ? 6 outputs are immediately asserted low and the pwm outputs are placed in the hard mute state. pdn initiates device power down without clock inputs. as long as the pdn terminal is held low ? the device is in the power-down (hard mute) state. during power down, all i 2 c and serial data bus operations are ignored. table 2 ? 8 shows the device output signals while pdn is active. table 2 ? 8. device outputs during power down signal mode signal state valid 1 ? valid 6 all low pwm p-outputs all low pwm m-outputs all low mclkout all low sclk master low sclk slave signal input lrclk master low lrclk slave signal input sda all signal input clip all high to place the device in total power-down mode, both reset and power-down modes must be enabled. prior to bringing pdn high, reset must be brought low for a minimum of 50 ns. because pdn is an asynchronous control signal, small clicks and pops can be produced during the application (the leading edge) of this control. however, when pdn is released, the transition from the hard mute state back to normal operation is performed synchronously using a quiet sequence. if a completely quiet reset sequence is desired, mute should be applied before applying pdn . 2.2.2.1 recovery time options to support the requirements of various system configurations, the TAS5026 can come up to the normal state after either a long (100 ms) or a short (5 ms) delay. 1. in the first case, a slow system (95 ms to 100 ms) start-up occurs at the end of the power-down sequence when: reset is high for at least 16 mclk_in periods before pdn goes high. 2. otherwise a fast (4 ms to 5 ms) start up occurs. note: if mclk_in is not active when both of these signals are released high, then a a fast (4 ms to 5 ms) start up occurs once mclk_in becomes active. 2.2.3 status registers the TAS5026 provides device identification and operational status information that is accessible through the serial control interface status registers that provide general device information. device id ? the TAS5026 provides a device identification code that is accessible through the serial control interface volume update is in progress ? whenever a volume change is in progress, this status bit is high. no internal errors (all valid signals are high) ? when there are no internal errors in the TAS5026 and all outputs are valid, this status bit is high. lrclk error ? when there are the mclk_in rate changes more than 10 mclk_in cycles from the correct number of cycles (128 or 256) per lrclk cycle mclk_in error ? when the mclk_in frequency changes such that it is out of synchronization with internal pll generated clock
architecture overview 17 sles041b ? november 2002 TAS5026 2.3 signal processing this section contains the signal processing functions that are contained in the TAS5026. the signal processing is performed using a high-speed 24-bit signal processing architecture. the TAS5026 performs the following signal processing features: ? individual channel soft volume with a range of 24 db to ? 114 db plus mute ? soft mute ? auto mute ? 50- s/15- s de-emphasis filter supported in the sampling rates 32 khz, 44.1 khz, and 48 khz 2.3.1 volume control the gain of each output can be adjusted by a soft digital volume control for each channel. volume adjustments are performed using a soft gain update s-curve, which is approximated using a second order filter fit. the curve fit is performed over a transition interval between 41 ms and 65 ms. the volume of each channel can be adjusted from mute to 24 db to ? 114 db in 0.5 db steps. because of the numerical representation that is used to control the volume, at very low volume levels the step size increases for gains of that are less than ? 96 db. the default volume setting following power up or reset is 0 db for all channels. the step size increases linearly up to approximately ? 90 db, see figure 2 ? 10. attenuation (gain) ? db 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ? 110 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 10 20 step size ? db step size vs attenuation (gain) figure 2 ? 10. attenuation curve the volume control format for each channel is expressed in 8 bits. the volume for each channel is set by writing 8 bits via the serial control interface. the msb bit is written first as in the bit position 0 (lsb position). the volume for each channel can be set using a single or multiple address write operation to the volume control register via the serial control interface. to change the volume of all six channels requires that 6 registers be updated. to coordinate the volume adjustment of multiple channels simultaneously, the TAS5026 performs a delayed volume update upon receiving a volume change command. following the completion of the register volume write operations, the TAS5026 waits for 5 ms for another volume command to be given. if no volume command is issued in that period of time, the TAS5026 starts adjusting the volume of the channels that received volume settings.
architecture overview 18 sles041b ? november 2002 TAS5026 while a volume update is being performed, the system status register indicates that the update is in progress. during the update, all subsequent volume control setting requests that are sent to the TAS5026 are received and stored as a single next value for a subsequent update. if more than one volume setting request is sent, only the last is retained. table 2 ? 9. volume register volume register d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 vol bit 7 vol bit 6 vol bit 5 vol bit 4 vol bit 3 vol bit 2 vol bit 1 vol bit 0 2.3.2 mute the application of mute ramps the volume from any setting to noiseless hard mute state. there are two methods in which the TAS5026 can be placed into mute. the TAS5026 is placed in the noiseless mute when the mute terminal is asserted low for a minimum of 3 mclk_in cycles. alternatively, the mute mode can be initiated by setting the mute bit in the system control register through the serial control interface. the TAS5026 is held in mute state as long as the terminal is low or i 2 c mute setting is active. this command uses quiet entry and exit sequences to and from the hard mute state. if an error recovery (described in the pwm section) occurs after a mute request has been received, the device returns from error recovery with the channel volume set as specified by the mute command. 2.3.3 auto mute auto mute is an automatic sequence that can be enabled or disabled via the serial control interface. the default for this control is enabled. when enabled, the pwm auto mutes an individual channel when a channel receives from 5 ms to 50 ms of consecutive zeros. this time interval can be selectable using the auto mute delay register. the default interval is 5 ms at 48 khz. this duration is independent of the sample rate. the auto mute state is exited when two consecutive samples of nonzero data are received. this mode uses the valid low to provide a low-noise floor while maintaining a short startup time. noise free entry and exit is achieved by using the pwm quiet start and stop sequences. 2.3.4 individual channel mute individual channel mute is invoked through the serial interface. individual channel mute permits each channel of the TAS5026 to be individually muted and unmuted. the operation that is performed is identical to the mute operation; however, it is performed on a per channel basis. a TAS5026 channel is held in the mute state as long as the serial interface mute setting for that channel is set. 2.3.5 de-emphasis filter for audio sources that have been pre-emphasized, a precision 50- s/15- s de-emphasis filter is provided to support the sampling rates of 32 khz, 44.1 khz, and 48 khz. see figure 2 ? 11 for a graph showing the de-emphasis filtering characteristics. de-emphasis is set using two bits in the system control register. table 2 ? 10. de-emphasis filter characteristics dem_sel2 (msb) dem_sel1 description 0 0 de-emphasis disabled 0 1 de-emphasis enabled for fs = 48 khz 1 0 de-emphasis enabled for fs = 44 khz 1 1 de-emphasis enabled for fs = 32 khz following the change of state of the de-emphasis bits, the pwm outputs go into the soft mute state. after 128 lrclk periods for initialization, the pwm outputs are driven to the normal (unmuted) mode.
architecture overview 19 sles041b ? november 2002 TAS5026 0 ? 10 response ? db 3.18 (50 s) 10.6 (15 s) f ? frequency ? khz de-emphasis figure 2 ? 11. de-emphasis filter characteristics 2.4 pulse width modulator (pwm) the TAS5026 contains six channels of high performance digital equibit pwm modulators that are designed to drive switching output stages (back ends) in both single-ended (se) and h-bridge (bridge tied load) configuration. the TAS5026 device uses noise shaping and sophisticated error correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. the pwm provides six pseudo-differential outputs to drive six monolithic power stages (such as tas5110) or six discrete differential power stages using of gate drivers (such as the tas5182) and mosfets in single-ended or bridged configurations. the TAS5026 also provides a high performance differential output that can be used to drive an external analog headphone amplifier. 2.4.1 clipping indicator the clipping output is designed to indicate clipping. when any of the six pwm outputs exceeds the maximum allowable amplitude, the clipping indicator is asserted. the clipping indicator is cleared every 10 ms. 2.4.2 error recovery error recovery is used to provide error management and to permit the pwm output to be reset while preserving all inter-volume, inter-channel delay, dc offsets, and the other internal settings. error recovery is initiated by bringing the err_rcvry terminal low for a minimum 5 mclk_in cycles or by setting the error recovery bit in control register 1. error recovery is a level sensitive signal. the device also performs an error recovery automatically: ? when the speed configuration is changed to normal, double, or quad speed ? following a change in the serial data bus interface configuration when err_rcvry is brought low, all valid signals go low, and the pwm-p and pwm-m outputs go low. if there are any pending speed configurations, these changes are then performed. when err_rcvry is brought high, a delay of 4 ms to 5 ms is performed before the system starts the output re-initialization sequence. after the initialization time, the TAS5026 begins normal operation. during error recovery, all controls and device settings that were not updated are maintained in their current configurations. to permit error recovery to be used to provide tas5100 error management and recovery, the delay between the start of (falling edge) error recovery and the falling edge of valid 1 though valid 6 is selectable. this delay can be selected to be either 6 s or 47 s. during error recovery all serial data bus operations are ignored. at the conclusion of the sequence, the error recovery register bit is returned to normal operation state. table 2 ? 11 shows the device output signal states while during error recovery. table 2 ? 11. device outputs during error recovery signal mode signal state valid 1 ? valid 6 all low
architecture overview 20 sles041b ? november 2002 TAS5026 pwm p-outputs all low pwm m-outputs all low mclkout all low sclk master low sclk slave signal input lrclk master low lrclk slave signal input sda all signal input clip all high the transitions are done using a quiet entrance and exit sequence to prevent pops and clicks. 2.4.3 individual channel error recovery individual channel error recovery is used to provide error management and to permit the pwm output to be turned off. error recovery is initiated by setting one or more of the six error recovery bits in the error recovery register to low. while the error recover bits are brought low, the valid signals goes to the low state. when the error recovery bits are brought high, a delay of 4 ms to 5 ms occurs before the channels are returned to normal operation. the delay between the falling edge of the error recover bit and the falling edge of valid 1 though valid 6 is selectable. this delay can be selected to be either 6 s or 47 s. the TAS5026 controls the relative timing of the pseudo-differential drive control signals plus the valid signal to minimize the production of system noise during error recovery operations. the transitions to valid low and valid high are done using an almost quiet entrance and exit sequence to prevent pops and clicks. 2.4.4 pwm dc-offset correction an 8-bit value can be programmed to each of the six pwm offset correction registers to correct for any offset present in the output stages. the offset correction is divided into 256 intervals with a total offset correction of 1.56% of full scale. the default value is zero correction represented by 00 (hex). these values can be changed at any time through the serial control interface. 2.4.5 inter-channel delay an 8-bit value can be programmed to each of the six pwm inter-channel delay registers to add a delay per channel from 0 to 255 clock cycles. the delays correspond to cycles of the high-speed internal clock, dclk (or alternatively the external pll clock frequency). each subsequent channel has a default value that is n dclks larger than the preceding channel. the default values are 0 for the first channel and 76 for each successive channel. these values can be updated upon power up through the serial control interface. this delay is generated in the pwm block with the appropriate control signals generated in the ctl block. these values can be changed at any time through the serial control interface. 2.4.6 pwm/h-bridge and discrete h-bridge driver interface the TAS5026 provides six pwm outputs, which are designed to drive switching output stages (back-ends) in both single-ended (se) and h-bridge (bridge tied load) configuration. the back-ends may be monolithic power stages (such as the tas5110) or six discrete differential power stages using gate drivers (such as the the tas55182) and mosfets in single-ended or bridged configurations. the tas5110 device is optimised for bridge tied load (btl) configurations. these devices require a pure differential pwm signal with a third signal (valid) to control the mute state. in the mute state, the tas5110 outa and outb are both low.
architecture overview 21 sles041b ? november 2002 TAS5026 one channel of TAS5026 pwm_ap pwm_am valid tas5110 outa outb ap am reset bp bm speaker figure 2 ? 12. pwm outputs and h-bridge driven in btl configuration 2.5 i 2 c serial control interface the TAS5026 has a bidirectional serial control interface that is compatible with the i 2 c (inter ic) bus protocol and supports both 100 kbps and 400 kbps data transfer rates for single and multiple byte write and read operations. this is a slave only device that does not support a multi-master bus environment or wait state insertion. the control interface is used to program the registers of the device and to read device status. the TAS5026 supports the standard-mode i 2 c bus operation (100 khz maximum) and the fast i 2 c bus operation (400 khz maximum). the TAS5026 performs all i 2 c operations without i 2 c wait cycles. the i 2 c bus employs two signals; sda (data) and scl (clock), to communicate between integrated circuits in a system. data is transferred on the bus serially one bit at a time. the address and data are transferred in byte (8 bit) format with the most significant bit (msb) transferred first. in addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. the bus uses transitions on the data terminal (sda) while the clock is high to indicate a start and stop conditions. a high-to-low transition on sda indicates a start, and a low-to-high transition indicates a stop. normal data bit transitions must occur within the low time of the clock period. these conditions are shown in figure 2 ? 13. the master generates the 7-bit slave address and the read/write (r/w) bit to open communication with another device and then waits for an acknowledge condition. the TAS5026 holds sda low during acknowledge clock period to indicate an acknowledgement. when this occurs, the master transmits the next byte of the sequence. each device is addressed by a unique 7-bit slave address plus r/w bit (1 byte). all compatible devices share the same signals via a bidirectional bus using a wired-and connection. i 2 c an external pullup resistor must be used for the sda and scl signals to set the high level for the bus. 7 bit slave address r/w 8 bit register address (n) aa 8 bit register data for address (n) a 8 bit register data for address (n) a 76543210 76543210 76543210 76543210 start stop sda scl figure 2 ? 13. typical i 2 c sequence there are no limits on the number of bytes that can be transmitted between start and stop conditions. when the last word transfers, the master generates a stop condition to release the bus. a generic data transfer sequence is also shown in figure 2 ? 13. the 7-bit address for the TAS5026 is 001101x, where x is a programmable address bit. using the cs0 terminal on the device, the lsb address bit is programmable to permit two devices to be used in a system. these two addresses are licensed i 2 c addresses and do not conflict with other licensed i 2 c audio devices. to communicate with the TAS5026, the i 2 c master uses 0011010 if cs0=0 and 0011011 if cs0=1. in addition to the 7-bit device address, an 8-bit register address is used to direct communication to the proper register location within the device interface.
architecture overview 22 sles041b ? november 2002 TAS5026 read and write operations to the TAS5026 can be done using single byte or multiple byte data transfers. 2.5.1 single byte write as shown in figure 2 ? 14, a single byte data write transfer begins with the master device transmitting a start condition followed by the i 2 c device address and the read/write bit. the read/write bit determines the direction of the data transfer. for a write data transfer, the read/write bit is 0. after receiving the correct i 2 c device address and the read/write bit, the TAS5026 device responds with an acknowledge bit. next, the master transmits the address byte or bytes corresponding to the TAS5026 internal memory address being accessed. after receiving the address byte, the TAS5026 again responds with an acknowledge bit. next, the master device transmits the data byte to be written to the memory address being accessed. after receiving the data byte, the TAS5026 again responds with an acknowledge bit. finally, the master device transmits a stop condition to complete the single byte data write transfer. a6 a5 a4 a3 a2 a1 a0 r/w ack a7 a6 a5 a4 a3 a2 a1 a0 ack d7 d6 d5 d4 d3 d2 d1 d0 ack start condition stop condition acknowledge acknowledge acknowledge i 2 c device address and read/write bit register address data byte figure 2 ? 14. single byte write transfer 2.5.2 multiple byte write a multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes are transmitted by the master device to TAS5026 as shown in figure 2 ? 15. after receiving each data byte, the TAS5026 responds with an acknowledge bit. d7 d6 d1 d0 ack stop condition acknowledge i 2 c device address and read/write bit register address last data byte a6 a5 a1 a0 r/w ack a7 a5 a1 a0 ack d7 d6 d1 d0 ack start condition acknowledge acknowledge acknowledge first data byte a4 a3 a6 other data bytes figure 2 ? 15. multiple byte write transfer 2.5.3 single byte read as shown in figure 2 ? 16, a single byte data read transfer begins with the master device transmitting a start condition followed by the i 2 c device address and the read/write bit. for the data read transfer, a write followed by a read are actually done. initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. as a result, the read/write bit is 0. after receiving the TAS5026 address and the read/write bit, the TAS5026 responds with an acknowledge bit. also, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5026 address and the read/write bit again. this time the read/write bit is a 1 indicating a read transfer. after receiving the TAS5026 and the read/write bit, the TAS5026 again responds with an acknowledge bit. next, the TAS5026 transmits the data byte from the memory address being read. after receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer. a6 a5 a0 r/w ack a7 a6 a5 a4 a0 ack a6 a5 a0 ack start condition stop condition acknowledge acknowledge acknowledge i 2 c device address and read/write bit register address data byte d7 d6 d1 d0 ack i 2 c device address and read/write bit repeat start condition not acknowledge r/w a1 a1 figure 2 ? 16. single byte read
architecture overview 23 sles041b ? november 2002 TAS5026 2.5.4 multiple byte read a multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes are transmitted by the TAS5026 to the master device as shown in figure 2 ? 17. except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. a6 a0 ack acknowledge i 2 c device address and read/write bit r/w a6 a0 r/w ack a4 a0 ack d7 d0 ack start condition stop condition acknowledge acknowledge acknowledge last data byte d7 d6 d1 d0 ack first data byte repeat start condition not acknowledge i 2 c device address and read/write bit register address other data bytes a7 a6 a5 figure 2 ? 17. multiple byte read
serial control interface register definitions 24 sles041b ? november 2002 TAS5026 3 serial control interface register definitions table 3 ? 1 shows the register map for the TAS5026. default values in this section are in bold. table 3 ? 1. i 2 c register map addr hex description 00 general status register 01 error status register 02 system control register 0 03 system control register 1 04 error recovery register 05 automute delay 06 dc-offset control register channel 1 07 dc-offset control register channel 2 08 dc-offset control register channel 3 09 dc-offset control register channel 4 0a dc-offset control register channel 5 0b dc-offset control register channel 6 0c interchannel delay register channel 1 0d interchannel delay register channel 2 0e interchannel delay register channel 3 0f interchannel delay register channel 4 10 interchannel delay register channel 5 11 interchannel delay register channel 6 12 reserved 13 volume control register channel 1 14 volume control register channel 2 15 volume control register channel 3 16 volume control register channel 4 17 volume control register channel 5 18 volume control register channel 6 19 individual channel mute the volume table is contained in appendix a. default values are shown in bold in the following tables note: the performance of a tdaa system is optimized by setting the pwm timing based upon the type of back-end device that is used and, to a lesser extent, the layout. these values are set during initialization using the i 2 c serial interface. the specific timing parameter values for each pwm and back-end configuration is contained in the evm user manual, reference design user manual, and design application note for these devices. please refer to the appropriate evm user manual, reference design user manual, or design application note for these values.
serial control interface register definitions 25 sles041b ? november 2002 TAS5026 3.1 general status register (x00) table 3 ? 2. general status register (read only) d7 d6 d5 d4 d3 d2 d1 d0 function 0 - - - - - - - no volume update is in progress. 1 - - - - - - - volume update is in progress. - 0 - - - - - - always 0 - - 1 0 0 1 1 - device identification code - - - - - - - 0 any valid signal is inactive (see status register (x03)) (see note 1). - - - - - - - 1 no internal errors (all valid signals are high) note 1: this bit is reset automatically when all of the valid signals are active. 3.2 error status register (x01) table 3 ? 3. error status register d7 d6 d5 d4 d3 d2 d1 d0 function 1 - - - - - - - fs error has occurred - 1 - - - - - - control pin change has occurred - - - 1 - - - - lrclk error - - - - 1 - - - mclk_in count error - - - - - 1 - - dclk phase error with respect to mclk_in - - - - - - 1 - mclk_in phase error with respect to dclk - - - - - - - 1 pwm timing error 0 0 0 0 0 0 0 0 no errors ? no control pins changed note 2: write 00 hex to clear error indications in error status register. 3.3 system control register 0 (x02) table 3 ? 4. system control register 0 d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 - - - - - - normal mode (in slave mode ? quad speed detected if mclk_in = 128 fs) 0 1 - - - - - - double speed 1 0 - - - - - - quad speed 1 1 - - - - - - illegal - - 0 - - - - - use de-emphasis pin controls - - 1 - - - - - use de-emphasis i2c controls - - - 0 0 - - - no de-emphasis - - - 0 1 - - - de-emphasis for fs = 32 khz - - - 1 0 - - - de-emphasis for fs = 44.1 khz - - - 1 1 - - - de-emphasis for fs = 48 khz - - - - - 0 0 0 16 bit, msb first; right justified - - - - - 0 0 1 20 bit, msb first; right justified - - - - - 0 1 0 24 bit, msb first; right justified - - - - - 0 1 1 16-bit iis - - - - - 1 0 0 20-bit iis - - - - - 1 0 1 24-bit iis - - - - - 1 1 0 16-bit msb first - - - - - 1 1 1 16-bit dsp frame
serial control interface register definitions 26 sles041b ? november 2002 TAS5026 3.4 system control register 1 (x03) table 3 ? 5. system control register 1 d7 d6 d5 d4 d3 d2 d1 d0 function 0 - - - - - - - unused - - - - - - - - - 0 - - - - - - valid remains high during auto mute. - 1 - - - - - - valid goes low during auto mute. - - 0 - - - - - valid remains high during mute. - - 1 - - - - - valid goes low during mute. - - - 0 - - - - mute - - - 1 - - - - normal mode - - - - 0 - - - set error recovery delay at 6 s - - - - 1 - - - set error recovery delay at 47 s - - - - - 0 - - error recovery (forces error recovery initialization sequence) - - - - - 1 - - normal mode - - - - - - 0 - auto mute disabled - - - - - - 1 - auto mute enabled - - - - - - - 0 normal mode - - - - - - - 1 resets all i 2 c registers to their default conditions 3.5 error recovery register (x04) table 3 ? 6. error recovery register d7 d6 d5 d4 d3 d2 d1 d0 function 1 1 - - - - - - unused - - - - - - - - - - 0 - - - - - put channel 6 into error recovery mode - - - 0 - - - - put channel 5 into error recovery mode - - - - 0 - - - put channel 4 into error recovery mode - - - - - 0 - - put channel 3 into error recovery mode - - - - - - 0 - put channel 2 into error recovery mode - - - - - - - 0 put channel 1 into error recovery mode - - 1 1 1 1 1 1 normal operation 3.6 automute delay register (x05) table 3 ? 7. automute delay register d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 - - - - unused - - - - - - - - - - - - 0 0 0 0 set automute delay at 5 ms - - - - 0 0 0 1 set automute delay at 10 ms - - - - 0 0 1 0 set automute delay at 15 ms - - - - 0 0 1 1 set automute delay at 20 ms - - - - 0 1 0 0 set automute delay at 25 ms - - - - 0 1 0 1 set automute delay at 30 ms - - - - 0 1 1 0 set automute delay at 35 ms - - - - 0 1 1 1 set automute delay at 40 ms - - - - 1 - - 0 set automute delay at 45 ms - - - - 1 - - 1 set automute delay at 50 ms
serial control interface register definitions 27 sles041b ? november 2002 TAS5026 3.7 dc-offset control registers (x06 ? x0b) channels 1, 2, 3, 4, 5, and 6 are mapped into (x06, x07, x08, x09, x0a, and x0b). table 3 ? 8. dc-offset control registers d7 d6 d5 d4 d3 d2 d1 d0 function 1 0 0 0 0 0 0 0 maximum correction for positive dc offset ( ? 1.56% fs) 0 0 0 0 0 0 0 0 no dc-offset correction 0 1 1 1 1 1 1 1 maximum correction for negative dc offset (1.56% fs) 3.8 interchannel delay registers (x0c ? x11) channels 1, 2, 3, 4, 5, and 6 are mapped into (x0c, x0d, x0e, x0f, x10, and x11). the first channel delay is set at 0. each subsequent channel has a default value that is 76 dclks larger than the preceding channel. table 3 ? 9. six inter-channel delay registers d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 0 0 0 0 minimum absolute delay, 0 dclk cycles, default for channel 1 0 0 0 1 0 0 0 0 default for channel 2 0 0 1 0 0 0 0 0 default for channel 3 0 0 1 1 0 0 0 0 default for channel 4 0 1 0 0 0 0 0 0 default for channel 5 0 1 0 1 0 0 0 0 default for channel 6 1 1 1 1 1 1 1 1 maximum absolute delay, 255 dclk cycles 3.9 individual channel mute register (x19) table 3 ? 10. individual channel mute register d7 d6 d5 d4 d3 d2 d1 d0 function 1 1 - - - - - - unused - - - - - - - - - - 1 1 1 1 1 1 no channels are muted - - - - - - - 0 mute channel 1 - - - - - - 0 - mute channel 2 - - - - - 0 - - mute channel 3 - - - - 0 - - - mute channel 4 - - - 0 - - - - mute channel 5 - - 0 - - - - - mute channel 6
system initialization 28 sles041b ? november 2002 TAS5026 4 system initialization reset is used during system initialization to hold the TAS5026 inactive while power (vdd), the master clock (mclk_in), the device control, and the data signals become stable. the recommended initialization sequence is to hold reset low for 24 mclk_in cycles after vdd has reached 3 v and the other control signals (mute , pdn , m_s, err_rcvry ,,dbspd, and cs0) are stable. mclk vdd 3 v 24 mclk_in cycles reset figure 4 ? 1. reset during system initialization the serial data interface format is then set through the serial data interface control register using the serial control interface. at this point the TAS5026 is fully operational. however, the operation of the TAS5026 can be tailored as desired to meet specific operating requirements by adjusting the following: ? automute delay register ? dc-offset control registers ? interchannel delay registers
specifications 29 sles041b ? november 2002 TAS5026 5 specifications 5.1 absolute maximum ratings over operating temperature ranges (unless otherwise noted) ? digital supply voltage range: dvdd_core, dvdd_pwm, dvdd_rcl ? 0.3 v to 4.2 v . . . . . . . . . . . . . . . . . . analog supply voltage range: avdd_pll, add_osc ? 0.3 v to 4.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital input voltage range, v i ? 0.3 v to dvddx + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature 0 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . esd 2000 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5.2 recommended operating conditions (fs = 48 khz) min typ max unit supply voltage digital dv ddx , see note 1 3 3.3 3.6 v supply current digital operating 60 ma supply current digital power down, see note 2 25 a power dissipation digital operating 200 mw power dissipation digital power down 100 w supply voltage analog av ddx , see note 3 3 3.3 3.6 v supply current analog operating 10 ma supply current analog power down, see note 2 25 a power dissipation analog operating 35 mw power dissipation analog power down, see note 2 100 w notes: 3. dvdd_core, dvdd_pwm, dvdd_rcl 4. if the clocks are turned off. 5. avdd_pll, avdd_osc 5.3 electrical characteristics over recommended operating conditions (unless otherwise noted) 5.3.1 static digital specifications over recommended operating conditions (unless otherwise noted) parameter test conditions min max unit v ih high-level input voltage 2 dvdd1 v v il low-level input voltage 0 0.8 v v oh high-level output voltage i o = ? 1 ma 2.4 v v ol low-level output voltage i o = 4 ma 0.4 v i lkg input leakage current ? 10 10 a 5.3.2 digital interpolation filter and pwm modulator over recommended operating conditions (unless otherwise noted) fs = 48 khz parameter test conditions min typ max unit pass band 0 20 khz pass band ripple 0.012 db stop band 24.1 khz stop band attenuation 24.1 khz to 152.3 khz 50 db group delay 700 s pwm modulation index (gain) 0.93
specifications 30 sles041b ? november 2002 TAS5026 5.3.3 TAS5026/tas5100 system performance measured at the speaker terminals over recommended operating conditions (unless otherwise noted) fs = 48 khz; input = 1 vrms sine wave at 1 khz parameter test conditions min typ max unit snr (eiaj) a-weighted 93 db dynamic range a-weighted, -60 db, f = 1 khz, 20 hz ? 20 khz 95 db signal to (noise + distortion) ratio 0 db, 1 khz, 20 hz ? 20 khz 0.08% pad driver power supply rejection ratio 1 khz db idle tone rejection db intermodulation distortion db frequency response db crosstalk db jitter tolerance ps pwm modulation index 0.93 5.4 switching characteristics 5.4.1 command sequence timing 5.4.1.1 reset timing ? reset control signal parameters over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit t w(reset) pulses duration, reset active 50 ns t p(valid_low) propagation delay 1 s t p(valid_high) propagation delay 4 5 ms t d(volume) delay time 42 ms t w(reset) t p(valid_high) reset t p(valid_low) t d(volume) valid 1 ? 6 volume 1 ? 6 figure 5 ? 1. reset timing
specifications 31 sles041b ? november 2002 TAS5026 5.4.1.2 power-down timing ? pdn 5.4.1.2.1 long recovery control signal parameters over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit t w(pdn) pulse duration, pdn active 50 ns t d(r pdnr) reset high to pdn rising edge 16 mclks ns t p(valid_low) 1 s t p(valid_high) 85 100 ms t d(volume) 42 ms reset t p(valid_low) valid 1 ? 6 volume 1 ? 6 pdn normal operation t d(r pdnr) t w(pdn) t p(valid_high) t d(volume) normal operation figure 5 ? 2. power-down and power-up timing ? reset preceding pdn
specifications 32 sles041b ? november 2002 TAS5026 5.4.1.2.2 short recovery control signal parameters over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit t w(pdn) pulse duration, pdn active 50 ns t d(r pdnr) pdn high to reset rising edge 16 mclks ns t p(valid_low) 1 s t p(valid_high) 4 5 ms t d(volume) 42 ms reset t p(valid_low) valid 1 ? 6 volume 1 ? 6 pdn normal operation t w(pdn) t p(valid_high) t d(volume) normal operation t d(r pdnr) figure 5 ? 3. power-down and power-up timing ? reset following pdn 5.4.1.3 error recovery timing ? err_rcvry control signal parameters over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit t w(er) pulse duration, err_rcvry active 5 mclks ns t p(valid_low) selectable for minimum or maximum 6 47 s t p(valid_high) 4 5 ms
specifications 33 sles041b ? november 2002 TAS5026 err_rcvry t p(valid_low) valid 1 ? 6 t w(er) t p(valid_high) normal operation normal operation figure 5 ? 4. error recovery timing 5.4.1.4 mute timing ? mute control signal parameters over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit t w(mute) pulse duration, pdn active 3 mclks ns t d(vol) 42 ms t d(vol) volume mute normal operation valid 1 ? 6 normal operation t d(vol) t w(mute) figure 5 ? 5. mute timing
specifications 34 sles041b ? november 2002 TAS5026 5.4.2 serial audio port 5.4.2.1 serial audio ports slave mode over recommended operating conditions (unless otherwise noted) parameter min typ max unit f (sclk) frequency, sclk 12.288 mhz t su(sdin) sdin setup time before sclk rising edge 20 ns t h(sdin) sdin hold time before sclk rising edge 10 ns f (lrclk) lrclk frequency 32 48 192 khz mclk_in duty cycle 50% sclk duty cycle 50% lrclk duty cycle 50% t su(lrclk) lrclk setup time before sclk rising edge 20 ns mclk high and low time 20 ns 5.4.2.2 serial audio ports master mode, load conditions 50 pf over recommended operating conditions (unless otherwise noted) parameter min typ max unit t (msd) mclk_in to sclk 0 5 ns t (mlrd) mclk_in to lrclk 0 5 ns 5.4.2.3 dsp serial interface mode over recommended operating conditions (unless otherwise noted) parameter min typ max unit f (sclk) sclk frequency 12.288 mhz t d(fs) delay time, sclk rising to fs ns t w(fshigh ) pulse duration, sync 1/(64xfs) ns t su(sdin) sdin and lrclk setup time before sclk falling edge 20 ns t h(sdin) sdin and lrclk hold time from sclk falling edge 10 ns sclk duty cycle 50% t h(sdin) t su(sdin) sclk sdin figure 5 ? 6. right-justified, iis, left-justified serial protocol timing
specifications 35 sles041b ? november 2002 TAS5026 t su(lrclk) sclk lrclk note: serial data is sampled with the rising edge of sclk (setup time = 20 ns and hold time = 10 ns). figure 5 ? 7. right, left, and iis serial mode timing requirement lrclk sclk mclk t (mrld) t (msd) figure 5 ? 8. serial audio ports master mode timing lrclk sclk sdin t su(lrclk) t h(lrclk) t w(fshigh) t su(sdin) t h(sdin) figure 5 ? 9. dsp serial port timing
specifications 36 sles041b ? november 2002 TAS5026 64 sclks sclk lrclk sdin 16 bits left channel 16 bits right channel 32 bits unused t w(fshigh) figure 5 ? 10. dsp serial port expanded timing sclk sdin t su(sdin) = 20 ns t h(sdin) = 10 ns figure 5 ? 11. dsp absolute timing
specifications 37 sles041b ? november 2002 TAS5026 5.4.3 serial control port ? i 2 c operation 5.4.3.1 timing characteristics for i 2 c interface signals over recommended operating conditions (unless otherwise noted) parameter test conditions standard mode fast mode unit parameter test conditions min max min max unit f scl frequency, scl 0 100 0 400 khz t w(h) pulse duration, scl high 4 0.6 s t w(l) pulse duration, scl low 4.7 1.3 s t r rise time, scl and sda 1000 300 ns t f fall time, scl and sda 300 300 ns t su1 setup time, sda to scl 250 100 ns t h1 hold time, scl to sda 0 0 ns t (buf) bus free time between stop and start condition 4.7 1.3 s t su2 setup time, scl to start condition 4.7 0.6 s t h2 hold time, start condition to scl 4 0.6 s t su3 setup time, scl to stop condition 4 0.6 s c l load capacitance for each bus line 400 400 pf sclk sda t h1 t w(l) t f t r t su t w(h) figure 5 ? 12. scl and sda timing sclk sda t h2 t (buf) t su2 t su3 start condition stop condition figure 5 ? 13. start and stop conditions timing
application information 38 sles041b ? november 2002 TAS5026 6 application information pwm ch. output control avdd_pll avss_pll vrega_cap vregb_cap vregc_cap dvdd_rcl dvss_rcl dvdd_pwm dvss_pwm power supply pll_flt_1 pll_flt_2 sclk lrclk mclkout sdin1 sdin2 sdin3 mclk_in xtal_out xtal_in css sda scl cso pwm_ap_1 valid_1 pwm_ap_2 valid_2 pwm ap_3 valid_3 pwm_ap_4 valid_4 pwm_ap_5 valid_5 pwm_ap_6 valid_6 pwm am_3 pwm_am_1 pwm_am_2 pwm_am_4 pwm_am_5 pwm_am_6 clock, pll and serial data i/f pdn reset mute clip err_rcvy serial control i/f reset, pwr dwn and status auto mute de-emphasis soft volume error recovery soft mute clip detect signal processing pwm section pwm ch. pwm ch. pwm ch. pwm ch. pwm ch. pwap pwbm pwam pwbp reset shutdown tas5110 h-bridge m_s da610 dsp clkout aclkx alkx1 alkx0 afsx alkx2 msp430 p1.5/ia1/tdi p1.0 p1.3 p1.1 p2.0 p1.4/smclk/tck p1.2 pwap pwbm pwam pwbp reset shutdown tas5110 h-bridge pwap pwbm pwam pwbp reset shutdown tas5110 h-bridge pwap pwbm pwam pwbp reset shutdown tas5110 h-bridge pwap pwbm pwam pwbp reset shutdown tas5110 h-bridge pwap pwbm pwam pwbp reset shutdown tas5110 h-bridge figure 6 ? 1. typical TAS5026 application
application information 39 sles041b ? november 2002 TAS5026 6.1 serial audio interface clock master and slave interface configuration 6.1.1 slave configuration TAS5026 (slave mode) sdin1 sdin2 sdin3 xtali xtalo da610 dsp (master mode) clkout afsx aclkr alkx0 alkx1 alkx2 aclkx afsr clkin alkr0 pcm1800 adc sysclk lrck dout bck left analog right analog alkr1 alkr2 other digital audio sources lrck sclk mclko 12.288 mhz xtal osci osco gnd nc mclko figure 6 ? 2. TAS5026 serial audio port ? slave mode connection diagram 6.1.2 master configuration TAS5026 (master mode) sdin1 sdin2 sdin3 xtali xtalo da610 dsp clkout afsx aclkr alkx0 alkx1 alkx2 aclkx afsr clkin alkr0 pcm1800 adc sysclk lrck dout bck left analog right analog alkr1 alkr2 other digital audio sources lrck sclk mclko 12.288 mhz xtal gnd mclko figure 6 ? 3. TAS5026 serial audio port ? master mode connection diagram
mechanical data 40 sles041b ? november 2002 TAS5026 7 mechanical data pag (s-pqfp-g64) plastic quad flatpack 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 4040282 / c 11/96 gage plane 33 0,17 0,27 16 48 1 7,50 typ 49 64 sq 9,80 1,05 0,95 11,80 12,20 1,20 max 10,20 sq 17 32 0,08 0,50 m 0,08 0 ? 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
appendix a ? volume table 41 sles041b ? november 2002 TAS5026 appendix a ? volume table volume setting register volume (bin) gain db d7 ? d0 249 1111 1001 24 248 1111 1000 23.5 247 11110111 23 246 11110110 22.5 245 11110101 22 244 11110100 21.5 243 11110011 21 242 11110010 20.5 241 11110001 20 240 11110000 19.5 239 11101111 19 238 11101110 18.5 237 11101101 18 236 11101100 17.5 235 11101011 170 234 11101010 16.5 233 11101001 16 232 11101000 15.5 231 11100111 15 230 11100110 14.5 229 11100101 14 228 11100100 13.5 227 11100011 13 226 11100010 12.5 225 11100001 12 224 11100000 11.5 223 11011111 11 222 11011110 10.5 221 11011101 10 220 11011100 9.5 219 11011011 9 218 11011010 8.5 217 11011001 8 216 11011000 7.5 215 11010111 7 214 11010110 6.5 213 11010101 6 212 11010100 5.5 211 11010011 5 210 11010010 4.5 209 11010001 4 208 11010000 3.5 207 11001111 3 206 11001110 2.5 volume setting register volume (bin) gain db d7 ? d0 205 11001101 2 204 11001100 1.5 203 11001011 1 202 11001010 0.5 201 11001001 0 200 11001000 ? 0.5 199 11000111 ? 1 198 11000110 ? 1.5 197 11000101 ? 2 196 11000100 ? 2.5 195 11000011 ? 3 194 11000010 ? 3.5 193 11000001 ? 4 192 11000000 ? 4.5 191 10111111 ? 5 190 10111110 ? 5.5 189 10111101 ? 6 188 10111100 ? 6.5 187 10111011 ? 7 186 10111010 ? 7.5 185 10111001 ? 8 184 10111000 ? 8.5 183 10110111 ? 9 182 10110110 ? 9.5 181 10110101 ? 10 180 10110100 ? 10.5 179 10110011 ? 11 178 10110010 ? 11.5 177 10110001 ? 12 176 10110000 ? 12.5 175 10101111 ? 13 174 10101110 ? 13.5 173 10101101 ? 14 172 10101100 ? 14.5 171 10101011 ? 15 170 10101010 ? 15.5 169 10101001 ? 16 168 10101000 ? 16.5 167 10100111 ? 17 166 10100110 ? 17.5 165 10100101 ? 18 164 10100100 ? 18.5 163 10100011 ? 19 162 10100010 ? 19.5
appendix a ? volume table 42 sles041b ? november 2002 TAS5026 volume setting register volume (bin) gain db d7 ? d0 161 10100001 ? 20 160 10100000 ? 20.5 159 1001 1111 ? 21 158 10011110 ? 21.5 157 10011101 ? 22 156 10011100 ? 22.5 155 10011011 ? 23 154 10011010 ? 23.5 153 10011001 ? 24 152 10011000 ? 24.5 151 10010111 ? 25 150 10010110 ? 25.5 149 10010101 ? 26 148 10010100 ? 26.5 147 10010011 ? 27 146 10010010 ? 27.5 145 10010001 ? 28 144 10010000 ? 28.5 143 10001111 ? 29 142 10001110 ? 29.5 141 10001101 ? 30 140 10001100 ? 30.5 139 10001011 ? 31 138 10001010 ? 31.5 137 10001001 ? 32 136 10001000 ? 32.5 135 10000111 ? 33 134 10000110 ? 33.5 133 10000101 ? 34 132 10000100 ? 34.5 131 10000011 ? 35 130 10000010 ? 35.5 129 10000001 ? 36 128 10000000 ? 36.5 127 01111111 ? 37 126 01111110 ? 37.5 125 01111101 ? 38 124 01111100 ? 38.5 123 01111011 ? 39 122 01111010 ? 39.5 121 01111001 ? 40 120 01111000 ? 40.5 119 01110111 ? 41 118 01110110 ? 41.5 117 01110101 ? 42 volume setting register volume (bin) gain db d7 ? d0 116 01110100 ? 42.5 115 01110011 ? 43 114 01110010 ? 43.5 113 01110001 ? 44 112 01110000 ? 44.5 111 01101111 ? 45 110 01101110 ? 45.5 109 01101101 ? 46 108 01101100 ? 46.5 107 01101011 ? 47 106 01101010 ? 47.5 105 01101001 ? 48 104 01101000 ? 48.5 103 01100111 ? 49 102 01100110 ? 49.5 101 01100101 ? 50 100 01100100 ? 50.5 99 01100011 ? 51 98 01100010 ? 51.5 97 01100001 ? 52 96 01100000 ? 52.5 95 0101 1111 ? 53 94 01011110 ? 53.5 93 01011101 ? 54 92 01011100 ? 54.5 91 01011011 ? 55 90 01011010 ? 55.5 89 01011001 ? 56 88 01011000 ? 56.5 87 01010111 ? 57 86 01010110 ? 57.5 85 01010101 ? 58 84 01010100 ? 58.5 83 01010011 ? 59 82 01010010 ? 59.5 81 01010001 ? 60 80 01010000 ? 60.5 79 01001111 ? 61 78 01001110 ? 61.5 77 01001101 ? 62 76 01001100 ? 62.5 75 01001011 ? 63 74 01001010 ? 63.5 73 01001001 ? 64 72 01001000 ? 64.5
appendix a ? volume table 43 sles041b ? november 2002 TAS5026 volume setting register volume (bin) gain db d7 ? d0 71 01000111 ? 65 70 01000110 ? 65.5 69 01000101 ? 66 68 01000100 ? 66.5 67 01000011 ? 67 66 01000010 ? 67.5 65 01000001 ? 68 64 01000000 ? 68.5 63 00111111 ? 69 62 00111110 ? 69.5 61 00111101 ? 70 60 00111100 ? 70.5 59 00111011 ? 71 58 00111010 ? 71.5 57 00111001 ? 72 56 00111000 ? 72.5 55 00110111 ? 73 54 00110110 ? 73.5 53 00110101 ? 74 52 00110100 ? 74.5 51 00110011 ? 75 50 00110010 ? 75.5 49 00110001 ? 76 48 00110000 ? 76.6 47 00101111 ? 77 46 00101110 ? 77.5 45 00101101 ? 78 44 00101100 ? 78.5 43 00101011 ? 79 42 00101010 ? 79.6 41 00101001 ? 80.1 40 00101000 ? 80.6 39 00100111 ? 81.1 38 00100110 ? 81.5 37 00100101 ? 82.1 volume setting register volume (bin) gain db d7 ? d0 36 00100100 ? 82.6 35 00100011 ? 83 34 00100010 ? 83.5 33 00100001 ? 84 32 00100000 ? 84.6 31 0001 1111 ? 85.1 30 00011110 ? 85.8 29 00011101 ? 86.1 28 00011100 ? 86.8 27 00011011 ? 87.2 26 00011010 ? 87.5 25 00011001 ? 88.4 24 00011000 ? 88.8 23 00010111 ? 89.3 22 00010110 ? 89.8 21 00010101 ? 90.3 20 00010100 ? 90.9 19 00010011 ? 91.5 18 00010010 ? 92.1 17 00010001 ? 92.8 16 00010000 ? 93.6 15 00001111 ? 94.4 14 00001110 ? 95.3 13 00001101 ? 96.3 12 00001100 ? 97.5 11 00001011 ? 98.8 10 00001010 ? 100.4 9 00001001 ? 102.4 8 00001000 ? 104.9 7 00000111 ? 108.4 6 00000110 ? 114.4 5 00000101 mute 4 00000100 mute 3 00000011 mute 2 00000010 mute 1 00000001 mute 0 00000000 mute

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